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One important consideration when designing electronics is to ensure that the electrical components operate at temperatures that will maintain long life and be reliable. Current carrying capacity of the printed circuit board traces is a part of managing the board temperature, which directly impacts the components. (A trace is a copper conductor in a printed circuit board.The terms conductor and trace are used interchangeably for a printed circuit throughout this chapter. Track is another common term for trace or conductor.) Properly sizing the traces for current is necessary to achieve the desired temperature rise at the board level. It is a difficult task to generalize current carrying capacity for all printed circuits and all applications. The only safe way to simplify this task is to overdesign. As technology requires pushing the limits on current levels, as well as using small trace widths and trace spacing, overdesigning is not a solution. Several sets of charts for sizing traces are presented in this chapter. These charts are explained and additional charts are presented. Thermal management of printed circuits often requires an accurate estimate of trace heating. This chapter presents information about conductor sizing charts and trace heating information as an aid to printed circuit design.

Charts are used to define the size of a trace for a given current level and temperature rise. The temperature rise of a trace is defined as the increase in temperature, above the local board temperature, that the trace reaches when current is flowing through it.The board temperature is similar to the ambient temperature when component power dissipations are low, although when the component power is several watts or more, the board temperature is significantly higher than the ambient temperature, especially in a still air or vacuum environment.

than go into their respective through-holes Sometimes solder from the HASL surface finish can redistribute during SMT reflow cycles, causing a bulging meniscus within the PTH This condition is depicted in Fig 496a Compare this illustration to that in Fig 496b, which shows a normally finished PTH with even wall FIGURE 496 Barrel profile as a result of surface coating, a relatively uniform barrel diameter, finish coating: (a) A PTH barrel with excess surface and an evenly coated primary-side annular finish from HASL, which has formed a meniscus ring With the advent of RoHS, HASL finishes upon solder reflow Other plating defects can result in such a meniscus, although the problem is uncommon are less common, but press-fit is commonly (b) A normal PTH barrel with evenly coated walls used in high-end servers and telecommunica- and annular rings.

(c) Excessive plating on PTH bartions equipment where the use of Sn-Pb solder rel walls and annular pads (d) Excess plating on is currently exempt from RoHS Pb-free annular ring causing pin interference and premature EON pin collapse (e) An overly compressed pin requirements excess PTH Excessive plating on PTH barrel walls and resulting from poses a plating onrisk annular ring This condition reliability annular pads (see Fig 496c, d) can cause premature collapse of the compliant section of the press-fit pin This condition may result in excessive pressing force to get the pin into the hole as well as insufficient normal contact force from the collapsed press-fit pin section to the barrel once fully seated in the hole This condition poses an electrical contact reliability risk, as shown in Fig 496e, where the pin is not actually in contact with the PTH barrel walls Figure 49.

7a shows a precollapsed press-fit pin that is making only intermittent contact due to the FIGURE 497 (a) Excess nickel plate on a PWB condition as depicted in Fig 497b PTH annular ring has caused two problems High-aspect-ratio holes (PWB thickness: PTH First, it has shaved material from the press-fit diameter) may have irregular plating where the thick- pin (arrows labeled x )Additionally, it caused ness closest to the board s outer layers is within compression of the compliant section of the acceptable thickness limits, whereas plating thickness pin When fully seated in the PTH, the pin was in the middle of the PTH may have unusually thin too loose for reliable contact The y labels deposits These thin deposits are caused by plating demark a gap between the press-fit pin and the PTH wall.

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